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PXA320 - 3 Host Ports Implementation

by D. Maheswari


Developers have been facing considerable issues with making 3 USB host ports work on XScale® PXA320. The development kits available in the market also do not seem to have three host ports working. To help developers, e-con Systems has come up with an article where it explains how to interface three USB host ports with Marvell PXA320(formerly Intel). The article also explains some of the problems faced while making the three USB host ports working with Windows CE 6.0 R2 on XScale PXA320 processor.


Why three host ports are required in any hand held application?
Three host ports can be required for various purposes to connect USB based Bluetooth module, USB based Wi-Fi implementation, to expose it as external mass storage, a biometric sensor or it can be used to collect data from sensor in data logging applications, etc
In the above said applications, XScale PXA320 can be used to implement three host ports. It is advantageous to use internal ports of a processor in terms of board real estate and in cost reduction perspective. But all the three ports in PXA320 are USB1.1 compatible only.
USB Implementation in Marvell PXA320 is such that host ports 1 & 3 can be used only as host ports, whereas port2 can be used either as host port 2 or OTG device. Currently standard development kits do not have the 3 host ports been implemented. For example, Zylonite, which is a Marvell's PXA320 Development kit does not have 3 host ports implemented.
In the discussion ahead it is clearly depicted how three host ports can be implemented. The article also discusses about the negatives of this approach


The XScale PXA320 USB host controller supports 3 USB Host ports.
Host Port 1: Host port with differential signals available at the output.
Host Port 2: Both single ended and differential signals are available.
Host Port 3: Only single ended signals are available.

Implementation of Host port 1

PXA320 gives differential D+ and D- signals using its internal transceiver. It also supplies power enable output and over current indication input for operating an external USB power switch. XScale PXA320 takes care of power supplied to external devices. On occurrence of over current indication, XScale PXA320 deasserts the power enable signal and hence cutting the power to USB device. This is taken care by PXA320 board itself.

Implementation of Host port 2

Second host port can be implemented in two modes:
  • Using internal transceiver.
  • Using external transceiver.
pxa320 Hostports
Fig:1 depicts the how 3 host ports can be implemented using PXA320.
Usage of internal transceiver is preferred to save real estate and Bill of Material cost.
The Internal non-OTG transceiver needs to be used to get differential host signals from PXA320. This can be implemented using UP2OCR register with HXOE =1; HXS = 1; SEOS = 0 and also enabling pull downs for D+ and D- Thus having the UP2OCR value as 0x3000C
In this case, since only USBHPEN2 is assigned as a dedicated to USB2_8 pin and USBPWR which is required to indicate over current need to be a GPIO, both the functions can be implemented as GPIO; thus USB bus powering functionality can be achieved. A Driver need to take care of enabling and disabling power to USB device in case of insertion of USB device or increased usage of Power by USB device.

Implementation of USB Port 3

USB Port3 is available only in single ended mode. Hence an external transceiver is necessary to implement the same. The external transceiver needs to understand the language of XScale PXA320 USB host Port3.
The tables below have the inputs and outputs expected from external transceiver for USB host port.
The output to external USB transceiver
P2_6/P3_6 P2_4/P3_4 Result
0 0 Logic 0
0 1 SE0
1 0 Logic 1
1 1 SE0
The inputs from external USB transceiver
P2_5/P3_5 P2_3/P3_3 Result
0 0 SEO0
0 1 Logic 0
1 0 Logic 1
TUSB1105 would be a good match with PXA320 and would work out well. Once a transceiver is selected, suspend and speed signals for the transceiver should be given through two GPIOs.
UP3OCR need to be configured to have the Host port 3 working. The CFG bits in UP3OCR is set to 0.
To enable USB bus powered applications, 2 GPIOs are needed to be allocated to take care of power enabling and disabling during normal and high load conditions. One needs to act as power-enable signal and another one needs to act as over current indication input. Power-enable signal needs to be deasserted on the assertion of over current indication.
Make sure the clocks that are supplied to the host controller are enabled to have the USB Host ports fully functional.

USB Interrupt configuration

UHC interrupts need to be configured to have three host ports working.
UHCINTE is the interrupt configuration register. UHCINTE register need to be configured so that interrupts are generated for the following events:
  • UHCDHEAD write back
  • Resume detect
  • Unrecoverable error
  • Frame number overflow
  • Hub status change
  • Master Interrupt enable
During system startup, Windows CE 6.0 R2 tries to gather information from the hardware on how many USB host ports are available. In case of PXA320, the hardware will return the number of ports as 2. The counting for PXA320 starts from zero and hence 2 means there are 3 USB host ports. For Windows CE, this number needs to be incremented by one to denote the number of host ports to 3. Though this would seem very simple, the lack of proper documentation has made this as a FAQ.


Testing can be done with various combinations of USB devices:
  • Keyboard, Mouse, Thumb drive
  • Keyboard, Mouse, USB card reader
  • Keyboard, USB Multi-card reader, Thumb drive
  • Mouse, USB Multi-card reader, Thumb drive
  • 3 Thumb drives


Please pass all your feedback and comments and also any questions you have to sales@e-consystems.com